1 tm file number 4846 caution: these devices are sensitive to electrostatic discharge. follow proper esd handling procedures. ultrafet is a trademark of intersil corporation. pspice is a trademark of microsim corporation. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright intersil corporation 2000 saber is a copyright of analogy inc. huf75852g3 75a, 150v, 0.016 ohm, n-channel, ultrafet power mosfet packaging jedec to-247 symbol features ultra low on-resistance -r ds(on) = 0.016 ?, v gs = 10v simulation models - temperature compensated pspice and saber electrical models - spice and saber thermal impedance models - www.intersil.com peak current vs pulse width curve uis rating curve source drain gate drain (tab) d g s ordering information part number package brand huf75852g3 to-247 75852g absolute maximum ratings t c = 25 o c, unless otherwise specified huf75852g3 units drain to source voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dss 150 v drain to gate voltage (r gs = 20k ? ) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr 150 v gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs 20 v drain current continuous (t c = 25 o c, v gs = 10v) (figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d continuous (t c = 100 o c, v gs = 10v) (figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d pulsed drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i dm 75 75 figure 4 a a pulsed avalanche rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .uis figures 6, 14, 15 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p d derate above 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 3.33 w w/ o c operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j , t stg -55 to 175 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .t l package body for 10s, see techbrief tb334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t pkg 300 260 o c o c note: 1. t j = 25 o c to 150 o c. caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. data sheet april 2000
2 electrical speci?ations t c = 25 o c, unless otherwise specified parameter symbol test conditions min typ max units off state specifications drain to source breakdown voltage bv dss i d = 250 a, v gs = 0v (figure 11) 150 - - v zero gate voltage drain current i dss v ds = 140v, v gs = 0v - - 1 a v ds = 135v, v gs = 0v, t c = 150 o c - - 250 a gate to source leakage current i gss v gs = 20v - - 100 na on state specifications gate to source threshold voltage v gs(th) v gs = v ds , i d = 250 a (figure 10) 2 - 4 v drain to source on resistance r ds(on) i d = 75a, v gs = 10v (figure 9) - 0.013 0.016 w thermal specifications thermal resistance junction to case r jc to-247 - - 0.30 o c/w thermal resistance junction to ambient r ja --30 o c/w switching specifications (v gs = 10v) turn-on time t on v dd = 75v, i d = 75a v gs = 10v, r gs = 2.0 ? (figures 18, 19) - - 260 ns turn-on delay time t d(on) -22-ns rise time t r - 151 - ns turn-off delay time t d(off) -82-ns fall time t f - 107 - ns turn-off time t off - - 285 ns gate charge specifications total gate charge q g(tot) v gs = 0v to 20v v dd = 75v, i d = 75a, i g(ref) = 1.0ma (figures 13, 16, 17) - 400 480 nc gate charge at 10v q g(10) v gs = 0v to 10v - 215 260 nc threshold gate charge q g(th) v gs = 0v to 2v - 15 17.5 nc gate to source gate charge q gs -25-nc gate to drain ?iller?charge q gd -66-nc capacitance specifications input capacitance c iss v ds = 25v, v gs = 0v, f = 1mhz (figure 12) - 7690 - pf output capacitance c oss - 1650 - pf reverse transfer capacitance c rss - 535 - pf source to drain diode speci?ations parameter symbol test conditions min typ max units source to drain diode voltage v sd i sd = 75a - - 1.25 v i sd = 35a - - 1.00 v reverse recovery time t rr i sd = 75a, di sd /dt = 100a/ s - - 260 ns reverse recovered charge q rr i sd = 75a, di sd /dt = 100a/ s - - 1830 nc huf75852g3
3 typical performance curves figure 1. normalized power dissipation vs case temperature figure 2. maximum continuous drain current vs case temperature figure 3. normalized maximum transient thermal impedance figure 4. peak current capability t c , case temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 175 0.2 0.4 0.6 0.8 1.0 1.2 125 150 20 40 60 80 50 75 100 125 150 0 25 i d , drain current (a) t c , case temperature ( o c) v gs = 10v 175 0.1 1 2 10 -4 10 -3 10 -2 10 -1 10 0 10 1 0.01 10 -5 t, rectangular pulse duration (s) z jc , normalized thermal impedance single pulse notes: duty factor: d = t 1 /t 2 peak t j = p dm x z jc x r jc + t c p dm t 1 t 2 duty cycle - descending order 0.5 0.2 0.1 0.05 0.01 0.02 100 2000 50 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 -5 i dm , peak current (a) t, pulse width (s) transconductance may limit current in this region t c = 25 o c i = i 25 175 - t c 150 for temperatures above 25 o c derate peak current as follows: 1000 v gs = 10v huf75852g3
4 figure 5. forward bias safe operating area note: refer to intersil application notes an9321 and an9322. figure 6. unclamped inductive switching capability figure 7. transfer characteristics figure 8. saturation characteristics figure 9. normalized drain to source on resistance vs junction temperature figure 10. normalized gate threshold voltage vs junction temperature typical performance curves (continued) 10 100 10 500 1000 1 1 100 s 10ms 1ms v ds , drain to source voltage (v) i d , drain current (a) limited by r ds(on) area may be operation in this t j = max rated t c = 25 o c single pulse 100 100 1000 0.01 0.1 1 10 i as , avalanche current (a) t av , time in avalanche (ms) t av = (l)(i as )/(1.3*rated bv dss - v dd ) if r = 0 if r 0 t av = (l/r)ln[(i as *r)/(1.3*rated bv dss - v dd ) +1] starting t j = 25 o c starting t j = 150 o c 10 0 50 100 150 200 234 56 i d , drain current (a) v gs , gate to source voltage (v) pulse duration = 80 s duty cycle = 0.5% max v dd = 15v t j = 175 o c t j = 25 o c t j = -55 o c 50 100 150 200 01 23 6 0 i d , drain current (a) v ds , drain to source voltage (v) v gs =5v v gs = 20v pulse duration = 80 s duty cycle = 0.5% max t c = 25 o c v gs = 10v v gs = 7v v gs = 6v 45 0.4 1.0 1.6 2.2 2.8 -80 -40 0 40 80 120 200 normalized drain to source t j , junction temperature ( o c) on resistance v gs = 10v, i d = 75a pulse duration = 80 s duty cycle = 0.5% max 160 0.4 0.8 1.0 1.2 -80 -40 0 40 80 120 200 normalized gate t j , junction temperature ( o c) v gs = v ds , i d = 250 a threshold voltage 0.6 160 huf75852g3
5 figure 11. normalized drain to source breakdown voltage vs junction temperature figure 12. capacitance vs drain to source voltage note: refer to intersil application notes an7254 and an7260. figure 13. gate charge waveforms for constant gate current typical performance curves (continued) 0.9 1.0 1.1 1.2 -80 -40 0 40 80 120 200 t j , junction temperature ( o c) normalized drain to source breakdown voltage i d = 250 a 160 100 1000 10000 20000 0.1 1.0 10 100 c, capacitance (pf) v ds , drain to source voltage (v) v gs = 0v, f = 1mhz c iss = c gs + c gd c oss ? c ds + c gd c rss = c gd 0 2 4 6 8 10 0 50 100 150 200 250 v gs , gate to source voltage (v) v dd = 75v q g , gate charge (nc) i d = 75a i d = 30a waveforms in descending order: test circuits and waveforms figure 14. unclamped energy test circuit figure 15. unclamped energy waveforms t p v gs 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 huf75852g3
6 figure 16. gate charge test circuit figure 17. gate charge waveforms figure 18. switching time test circuit figure 19. switching time waveform test circuits and waveforms (continued) r l v gs + - v ds v dd dut i g(ref) v dd q g(th) v gs = 2v q g(10) v gs = 10v q g(tot) v gs = 20v v ds v gs i g(ref) 0 0 q gs q gd v gs r l r gs dut + - v dd v ds v gs t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 huf75852g3
7 pspice electrical model .subckt huf75852 2 1 3 ; rev 26 oct 1999 ca 12 8 12.0e-9 cb 15 14 12.0e-9 cin 6 8 7.15e-9 dbody 7 5 dbodymod dbreak 5 11 dbreakmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 159.2 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evthres 6 21 19 8 1 evtemp 20 6 18 22 1 it 8 17 1 ldrain 2 5 1.0e-9 lgate 1 9 7.46e-9 lsource 3 7 3.87e-9 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 9.50e-3 rgate 9 20 0.80 rldrain 2 5 10 rlgate 1 9 74.6 rlsource 3 7 38.7 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rsourcemod 2.37e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51)/abs(v(5,51)))*(pwr(v(5,51)/(1e-6*245),2.5))} .model dbodymod d (is = 6.03e-12 rs = 2.17e-3 trs1 = 1.97e-3 trs2 = 1.03e-6 cjo = 7.91e-9 tt = 1.69e-7 m = 0.60) .model dbreakmod d (rs = 3.53e-1 trs1 = 0 trs2 = 0) .model dplcapmod d (cjo = 9.52e-9 is = 1e-30 n = 1 m = 0.88) .model mmedmod nmos (vto = 3.05 kp = 8.50 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 0.80) .model mstromod nmos (vto = 3.53 kp = 215 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model mweakmod nmos (vto = 2.63 kp = 0.075 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 8.0 ) .model rbreakmod res (tc1 = 1.12e-3 tc2 = -1.00e-7) .model rdrainmod res (tc1 = 1.03e-2 tc2 = 3.04e-5) .model rslcmod res (tc1 = 2.52e-3 tc2 = 0) .model rsourcemod res (tc1 = 1.01e-3 tc2 = 0) .model rvthresmod res (tc1 = -3.65e-3 tc2 = -1.55e-5) .model rvtempmod res (tc1 = -2.85e-3 tc2 = 0) .model s1amod vswitch (ron = 1e-5 roff = 0.1 von = -3.5 voff= -3.0) .model s1bmod vswitch (ron = 1e-5 roff = 0.1 von = -3.0 voff= -3.5) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = -2.5 voff= -0.5) .model s2bmod vswitch (ron = 1e-5 roff = 0.1 von = -0.5 voff= -2.5) .ends note: for further discussion of the pspice model, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; ieee power electronics specialist conference records, 1991, written by william j. hepp and c. frank wheatley. 18 22 + - 6 8 + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 huf75852g3
8 saber electrical model rev 26 oct 1999 template huf75852 n2,n1,n3 electrical n2,n1,n3 { var i iscl d..model dbodymod = (is = 6.03e-12, cjo = 7.91e-9, tt = 1.69e-7, m = 0.60) d..model dbreakmod = () d..model dplcapmod = (cjo = 9.52e-9, is = 1e-30, n=1, m = 0.88 ) m..model mmedmod = (type=_n, vto = 3.05, kp = 8.50, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.53, kp = 215, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 2.63, kp = 0.075, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -3.5, voff = -3) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -3, voff = -3.5) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -2.5, voff = -0.5) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = -2.5) c.ca n12 n8 = 12.0e-9 c.cb n15 n14 = 12.0e-9 c.cin n6 n8 = 7.15e-9 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1.0e-9 l.lgate n1 n9 = 7.46e-9 l.lsource n3 n7 = 3.87e-9 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 1.12e-3, tc2 = -1.00e-7 res.rdbody n71 n5 = 2.17e-3, tc1 = 1.97e-3, tc2 = 1.03e-6 res.rdbreak n72 n5 = 3.53e-1, tc1 = 0, tc2 = 0 res.rdrain n50 n16 = 9.50e-3, tc1 = 1.03e-2, tc2 = 3.04e-5 res.rgate n9 n20 = 0.80 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 74.6 res.rlsource n3 n7 = 38.7 res.rslc1 n5 n51 = 1e-6, tc1 = 2.52e-4, tc2 = 0 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 2.37e-3, tc1 = 1.01e-3, tc2 = 0 res.rvtemp n18 n19 = 1, tc1 = -2.85e-3, tc2 = 0 res.rvthres n22 n8 = 1, tc1 = -3.65e-3, tc2 = -1.55e-5 spe.ebreak n11 n7 n17 n18 = 159.2 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/245))** 2.5)) } } 18 22 + - 6 8 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap iscl rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 rdbody rdbreak 72 71 huf75852g3
9 spice thermal model rev 19 oct 1999 huf75852t ctherm1 th 6 9.75e-3 ctherm2 6 5 3.90e-2 ctherm3 5 4 2.50e-2 ctherm4 4 3 2.95e-2 ctherm5 3 2 6.55e-2 ctherm6 2 tl 12.55 rtherm1 th 6 1.96e-3 rtherm2 6 5 4.89e-3 rtherm3 5 4 1.38e-2 rtherm4 4 3 7.73e-2 rtherm5 3 2 1.17e-1 rtherm6 2 tl 1.55e-2 saber thermal model saber thermal model huf75852t template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 9.75e-3 ctherm.ctherm2 6 5 = 3.90e-2 ctherm.ctherm3 5 4 = 2.50e-2 ctherm.ctherm4 4 3 = 2.95e-2 ctherm.ctherm5 3 2 = 6.55e-2 ctherm.ctherm6 2 tl = 12.55 rtherm.rtherm1 th 6 = 1.96e-3 rtherm.rtherm2 6 5 = 4.89e-3 rtherm.rtherm3 5 4 = 1.38e-2 rtherm.rtherm4 4 3 = 7.73e-2 rtherm.rtherm5 3 2 = 1.17e-1 rtherm.rtherm6 2 tl = 1.55e-2 } rtherm4 rtherm6 rtherm5 rtherm3 rtherm2 rtherm1 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 tl 2 3 4 5 6 th junction case huf75852g3
10 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (321) 724-7000 fax: (321) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 huf75852g3 to-247 3 lead jedec style to-247 plastic package a b b 1 c d e l l 1 r 1 2 e 1 3 1 j 1 s q p back view term. 4 3 e b 2 2 symbol inches millimeters notes min max min max a 0.180 0.190 4.58 4.82 - b 0.046 0.051 1.17 1.29 2, 3 b 1 0.060 0.070 1.53 1.77 1, 2 b 2 0.095 0.105 2.42 2.66 1, 2 c 0.020 0.026 0.51 0.66 1, 2, 3 d 0.800 0.820 20.32 20.82 - e 0.605 0.625 15.37 15.87 - e 0.219 typ 5.56 typ 4 e 1 0.438 bsc 11.12 bsc 4 j 1 0.090 0.105 2.29 2.66 5 l 0.620 0.640 15.75 16.25 - l 1 0.145 0.155 3.69 3.93 1 p 0.138 0.144 3.51 3.65 - q 0.210 0.220 5.34 5.58 - r 0.195 0.205 4.96 5.20 - s 0.260 0.270 6.61 6.85 - notes: 1. lead dimension and ?ish uncontrolled in l 1 . 2. lead dimension (without solder). 3. add typically 0.002 inches (0.05mm) for solder coating. 4. position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension d. 5. position of lead to be measured 0.100 inches (2.54mm) from bottom of dimension d. 6. controlling dimension: inch. 7. revision 1 dated 1-93.
|
